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职位描述/要求:
Responsibilities: 1. Layout floor planning; physical layout; routing; and verification including DRC; LVS; and LPE. 2. Provide layout techniques to improve circuit performance. 3. Work with design team to define optimal layout solutions based on design objectives.
General Requirements: 1.BS degree or equivalent with 2 years of semiconductor layout experience. 2.Experience in analog IC layout and Cadence IC Layout tool set. 3. Team-based; cross-functional organizational structure experience preferred. 4.Excellent interpersonal; Organizational; verbal; and written communication skills both in English and Chinese. 5.Willing to travel to USA may be needed.
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